ANNA UNIVERSITY ECE SYLLABUS
EC6612 VLSI DESIGN LABORATORY SYLLABUS
6TH SEM ECE SYLLABUS
REGULATION 2013
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| EC6612 VLSI DESIGN LABORATORY SYLLABUS |
OBJECTIVES:
- To learn Hardware Descriptive Language(Verilog/VHDL)
- To learn the fundamental principles of VLSI circuit design in digital and analog domain
- To familiarise fusing of logical modules on FPGAs
- To provide hands on design experience with professional design (EDA) platforms.
- To learn Hardware Descriptive Language(Verilog/VHDL)
- To learn the fundamental principles of VLSI circuit design in digital and analog domain
- To familiarise fusing of logical modules on FPGAs
- To provide hands on design experience with professional design (EDA) platforms.
LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS.
1. HDL based design entry and simulation of simple counters, state machines, adders (min 8 bit) and multipliers (4 bit min).
2. Synthesis, P&R and post P&R simulation of the components simulated in (I) above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs. IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier. Measure gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and resimulation of the circuit designed in (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above. Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R simulation. 8. Analysis of results of static timing analysis.
2. Synthesis, P&R and post P&R simulation of the components simulated in (I) above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs. IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier. Measure gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and resimulation of the circuit designed in (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above. Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R simulation. 8. Analysis of results of static timing analysis.
TOTAL: 45 PERIODS
OUTCOMES:
At the end of the course, the student should be able to
Write HDL code for basic as well as advanced digital integrated circuits.
Import the logic modules into FPGA Boards.
Synthesize, Place and Route the digital IPs.
Design, Simulate and Extract the layouts of Analog IC Blocks using EDA tools.
LAB EQUIPMENT FOR A BATCH OF 30 STUDENSTS:
Xilinx or Altera FPGA 10 nos
Xilinx software
Cadence/MAGMA/Tanner or equivalent software package 10 User License
PCs 10 No.s
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