EC6005 ELECTRONIC TESTING SYLLABUS FOR 7TH SEM ECE REGULATION 2013 - Anna University Internal marks 2018

EC6005 ELECTRONIC TESTING SYLLABUS FOR 7TH SEM ECE REGULATION 2013

 ANNA UNIVERSITY ECE SYLLABUS
EC6005 ELECTRONIC TESTING SYLLABUS
7TH SEM ECE SYLLABUS
REGULATION 2013
EC6005 ELECTRONIC TESTING SYLLABUS
EC6005 ELECTRONIC TESTING SYLLABUS
OBJECTIVES:
 To understand the basics of testing and the testing equipments
To understand the different testing methods 

UNIT I INTRODUCTION
Test process and automatic test equipment, test economics and product quality, fault modeling

UNIT II DIGITAL TESTING
Logic and fault simulation, testability measures, combinational and sequential circuit test generation.

UNIT III ANALOG TESTING
Memory Test, DSP Based Analog and Mixed Signal Test, Model based analog and mixed signal test, delay test, IIDQ test.

UNIT IV DESIGN FOR TESTABILITY
Built-in self-test, Scan chain design, Random Logic BIST, Memory BIST, Boundary scan test standard, Analog test bus, Functional Microprocessor Test, Fault Dictionary, Diagnostic Tree, Testable System Design, Core Based Design and Test Wrapper Design, Test design for SOCs

UNIT VLOADED BOARD TESTING
Unpowered short circuit tests, unpowered analog tests, Powered in-circuit analog, digital and mixed signal tests, optical and X-ray inspection procedures, functional block level design of in-circuit test equipment

TOTAL: 45 PERIODS

OUTCOMES:
Upon completion of the course, students
 Explain different testing equipments.
 Design the different testing schemes for a circuit.
 Discuss the need for test process

TEXT BOOK:
1. Michael L. Bushnell and Vishwani D. Agarwal, “Essentials of Electronic Testing for Digital,
Memory & Mixed-Signal VLSI Circuits”, Springer, 2006.

REFERENCE:
1. Dimitris Gizopouilos , “Advances in Electronic Testing” , Springer 2006.

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