EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY SYLLABUS REG-2013 FOR 3RD SEM ECE DEPARTMENT - Anna University Internal marks 2018

EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY SYLLABUS REG-2013 FOR 3RD SEM ECE DEPARTMENT

EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY SYLLABUS FOR ANNA UNIVERSITY THIRD SEMESTER ELECTRICAL AND COMMUNICATION ENGINEERING ECE DEPARTMENT STUDENTS
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY SYLLABUS
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY
  • University : Anna university
  • Semester : 3rd sem
  • Department : ECE
  • Year : Second Yr
  • Regulation : 2013
  • Subject Name : ANALOG AND DIGITAL CIRCUITS LABORATORY
  • Subject Code : EC6311 
  • Subject Credits : 2
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY SYLLABUS
SYLLABUS
REGULATION 2013
OBJECTIVES:

The student should be made to:
Study the characteristic of CE,CB and CC Amplifier
Learn the frequency response of CS Amplifiers
Study the Transfer characteristic of differential amplifier
Perform experiment to obtain the bandwidth of single stage and multistage amplifiers
Perform Spice simulation of electronics circuits

LIST OF EXPERIMENTS

LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurment
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers

LIST OF DIGITAL EXPERIMENTS
9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa

10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

TOTAL: 45 PERIODS

OUTCOMES:
At the end of the course, the student should be able to:
  • Differentiate cascade and cascade amplifier.
  • Analyze the limitation in bandwidth of single stage and multi  stage amplifier
  • Simulate amplifiers using Spice
  • Measure CMRR in differential amplifier
LAB REQUIREMENT FOR A BATCH OF 30 STUDENTS, 2 STUDENTS / EXPERIMENT:

Equipments for Analog Lab

CRO (30MHz) – 15 Nos.
Signal Generator /Function Generators (3 MHz) – 15 Nos
Dual Regulated Power Supplies ( 0 – 30V) – 15 Nos.
Standalone desktop PCs with SPICE software – 15 Nos.
Transistor/FET (BJT-NPN-PNP and NMOS/PMOS) – 50 Nos
Components and Accessories

Equipments for Digital Lab
Dual power supply/ single mode power supply - 15 Nos
IC Trainer Kit - 15 Nos
Bread Boards -15 Nos
Computer with HDL software - 15 Nos
Seven segment display -15 Nos
Multimeter -15 Nos
ICs each 50 Nos
7400/ 7402 / 7404 / 7486 / 7408 / 7432 / 7483 / 74150 / 74151 / 74147 / 7445 / 7476/7491/ 555 / 7494 / 7447 / 74180 / 7485 / 7473 / 74138 / 7411 / 7474

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