EC6302 DIGITAL ELECTRONICS SYLLABUS REG-2013 FOR 3RD SEM ECE DEPARTMENT

EC6302 DIGITAL ELECTRONICS SYLLABUS FOR ANNA UNIVERSITY THIRD SEMESTER ELECTRICAL AND COMMUNICATION ENGINEERING ECE DEPARTMENT STUDENTS

EC6302 DIGITAL ELECTRONICS SYLLABUS

• University : Anna university
• Semester : 3rd sem
• Department : ECE
• Year : Second Yr
• Regulation : 2013
• Subject Name : DIGITAL ELECTRONICS SYLLABUS
• Subject Code : EC6302 
• Subject Credits : 3

EC6302 DIGITAL ELECTRONICS SYLLABUS

SYLLABUS

REGULATION 2013

OBJECTIVES:

• To introduce basic postulates of Boolean algebra and shows the correlation between Boolean expressions.
• To introduce the methods for simplifying Boolean expressions
• To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits.
• To introduce the concept of memories and programmable logic devices.
• To illustrate the concept of synchronous and asynchronous sequential circuits

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions – Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations of Logic Functions using gates, NAND–NOR implementations – Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics – Tristate gates

UNIT II COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary adder,parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity checker – parity generators – code converters - Magnitude Comparator.

UNIT III SEQUENTIAL CIRCUITS

Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter – Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of Synchronous counters: state diagram- State table –State minimization –State assignment - Excitation table and maps-Circuit implementation - Modulo–n counter, Registers – shift registers - Universal shift registers – Shift register counters – Ring counter – Shift counters - Sequence generators.

UNIT IV MEMORY DEVICES

Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM –EAPROM,RAM – RAM organization – Write operation – Read operation – Memory cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell- Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL

UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits: General Model – Classification – Design – Use of Algorithmic State Machine – Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits – Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG.

TOTAL: 45 PERIODS

OUTCOMES:

Students will be able to:

• Analyze different methods used for simplification of Boolean expressions.
• Design and implement Combinational circuits.
• Design and implement synchronous and asynchronous sequential circuits.
• Write simple HDL codes for the circuits.

TEXT BOOK:

1. M. Morris Mano, “Digital Design”, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson

Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:

1. John F.Wakerly, “Digital Design”, Fourth Edition, Pearson/PHI, 2008

2. John.M Yarbrough, “Digital Logic Applications and Design”, Thomson Learning, 2006.

3. Charles H.Roth. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013.

4. Donald P.Leach and Albert Paul Malvino, “Digital Principles and Applications”, 6th Edition, TMH, 2006.

5. Thomas L. Floyd, “Digital Fundamentals”, 10th Edition, Pearson Education Inc, 2011

6. Donald D.Givone, “Digital Principles and Design”, TMH, 2003.