AP7102 ADVANCED DIGITAL LOGIC SYSTEM DESIGN - ANNA UNIVERSITY REGULATION 2013 PG SYLLABUS

ANNA UNIVERSITY, CHENNAI

AFFILIATED INSTITUTIONS

REGULATIONS - 2013

M.E. APPLIED ELECTRONICS
SEMESTER - 1 SYLLABUS

AP7102                ADVANCED DIGITAL LOGIC SYSTEM DESIGN           L T P C
                                                                                                                  3 0 0 3
OBJECTIVES:
 To analyze synchronous and asynchronous sequential circuits
 To realize and design hazard free circuits
 To familiarize the practical issues of sequential circuit design
 To gain knowledge about different fault diagnosis and testing methods
 To estimate the performance of digital systems
 To know about timing analysis of memory and PLD

UNIT I SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Clocked Synchronous Sequential Networks (CSSN) - Modeling of CSSN –
State Assignment and Reduction – Design of CSSN – Design of Iterative Circuits
– ASM Chart – ASM Realization, Design of Arithmetic circuits for Fast adder- Array
Multiplier.

UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9
Analysis of Asynchronous Sequential Circuit (ASC) – Flow Table Reduction – Races in
ASC – State Assignment Problem and the Transition Table – Design of ASC – Static
and Dynamic Hazards – Essential Hazards – Design of Hazard free circuits - Data
Synchronizers – Designing Vending Machine Controller – Mixed Operating Mode Asynchronous Circuits. Practical issues such as clock skew, synchronous and asynchronous inputs and switch bouncing.

UNIT III FAULT DIAGNOSIS & TESTING 9
Fault diagnosis: Fault Table Method – Path Sensitization Method – Boolean Difference Method
– Kohavi Algorithm – Tolerance Techniques – The Compact Algorithm. Design for testability:
Test Generation – Masking Cycle – DFT Schemes. Circuit testing fault model, specific and
random faults, testing of sequential circuits, Built in Self Test, Built in Logic Block observer
(BILBO), signature analysis.

UNIT IV PERFORMANCE ESTIMATION 9
Estimating digital system reliability, transmission lines, reflections and terminations, system
integrity, network issues for digital systems, formal verifications of digital system: modelchecking,binary decision diagram, theorem proving, circuit equivalence.

UNIT V TIMING ANALYSIS 9
ROM timings, Static RAM timing, Synchronous Static RAM and it’s timing, Dynamic RAM timing,Complex Programmable Logic Devices, Logic Analyzer Basic Architecture, Internal structure,
Data display, Setup and Control, Clocking and Sampling. 

TOTAL:45 PERIODS

REFERENCES:
1. Charles H.Roth Jr “Fundamentals of Logic Design”, Thomson Learning 2004.
2. Nripendra N Biswas “Logic Design Theory” Prentice Hall of India, 2001.
3. Parag K.Lala “An introduction to Logic Circuit Testing” Morgan and claypool publishers, 2009.
4. Stephen D Brown, “Fundamentals of digital logic”, TMH publication, 2007.
5. Balabanian, “Digital Logic Design Principles”, Wiley publication, 2007.
6. Stalling, “Computer Organization & Architecture”, Pearson Education India, 2008.
7. J.F.Wakerly, “Digital Design”, Pearson Education India, 2012.
8. J.F.Wakerly, “Digital Design principles and practices”, PHI publications, 2005.
9. Charles J. Sipil, Microcomputer Handbook McCrindle- Collins Publications 1977.