EC2203 DIGITAL ELECTRONICS ANNA UNIVERSITY PREVIOUS YEAR
QUESTION PAPER, IMPORTANT QUESTIONS, 2 MARKS AND 16 MARKS QUESTIONS FOR ECE
DEPARTMENT
2. Show that a positive logic NAND gate is a negative logic NOR gate.
3. Suggest a solution to overcome the limitation on the speed of an adder.
4. Differentiate a decoder from a demultiplexer.
5. Write down the characteristic equation for JK flipflop.
6. Distinguish between synchronous and asynchronous sequential circuits.
7. Compare and contrast static RAM and dynamic RAM.
8. What is PAL? How does it differ from PLA?
9. What are Hazards?
10. Compare the ASM chart with a conventional flow chart.
(6)
(ii) Reduce the following function using K-map technique
( ) ( ) ( ) 6 , 2 14 , 12 , 10 , 8 , 7 , 4 , 3 , 0 , , , d D C B A f + = π . (10)
Or
(b) Simplify the following Boolean function by using Quine-Mcclusky method
( ) ( ) ∑ = 13 , 12 , 10 , 8 , 7 , 6 , 3 , 2 , 0 , , , D C B A F . (16)
12. (a) Design a carry look ahead adder with necessary diagrams. (16)
Or
(b) (i) Implement full subtractor using demultiplexer. (10)
(ii) Implement the given Boolean function using 8 : 1 multiplexer
( ) ( ) ∑ = 6 , 5 , 3 , 1 , , C B A F . (6)
13. (a) (i) How will you convert a D flipflop into JK flipflop? (8)
(ii) Explain the operation of a JK master slave flipflop. (8)
Or
(b) Explain in detail the operation of a 4 bit binary ripple counter. (16)
14. (a) Implement the following Boolean functions with a PLA
( ) ( ) ∑ = 4 , 2 , 1 , 0 , , 1 C B A F
( ) ( ) ∑ = 7 , 6 , 5 , 0 , , 2 C B A F
( ) ( ) ∑ = 7 , 5 , 3 , 0 , , 3 C B A F . (16)
Or
(b) Design a combinational circuit using a ROM. The circuit accepts a three
bit number and outputs a binary number equal to the square of the input
number. (16)
15. (a) Design a three bit binary counter using T flipflops. (16)
Or
(b) Design a negative-edge triggered ‘T flipflop’. (16)
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER
2009.
Third
Semester
Electronics and Communication Engineering
EC 2203 —
DIGITAL ELECTRONICS
(Regulation 2008)
Time :
Three hours Maximum : 100 Marks
Answer
ALL Questions
PART A —
(10 × 2 = 20 Marks)
1. Prove
that the logical sum of all minterms of a Boolean function of 2
variables is 1.2. Show that a positive logic NAND gate is a negative logic NOR gate.
3. Suggest a solution to overcome the limitation on the speed of an adder.
4. Differentiate a decoder from a demultiplexer.
5. Write down the characteristic equation for JK flipflop.
6. Distinguish between synchronous and asynchronous sequential circuits.
7. Compare and contrast static RAM and dynamic RAM.
8. What is PAL? How does it differ from PLA?
9. What are Hazards?
10. Compare the ASM chart with a conventional flow chart.
PART B —
(5 × 16 = 80 Marks)
11. (a)
(i) Express the Boolean function Z X XY F + = in product of
Maxterm.(6)
(ii) Reduce the following function using K-map technique
( ) ( ) ( ) 6 , 2 14 , 12 , 10 , 8 , 7 , 4 , 3 , 0 , , , d D C B A f + = π . (10)
Or
(b) Simplify the following Boolean function by using Quine-Mcclusky method
( ) ( ) ∑ = 13 , 12 , 10 , 8 , 7 , 6 , 3 , 2 , 0 , , , D C B A F . (16)
12. (a) Design a carry look ahead adder with necessary diagrams. (16)
Or
(b) (i) Implement full subtractor using demultiplexer. (10)
(ii) Implement the given Boolean function using 8 : 1 multiplexer
( ) ( ) ∑ = 6 , 5 , 3 , 1 , , C B A F . (6)
13. (a) (i) How will you convert a D flipflop into JK flipflop? (8)
(ii) Explain the operation of a JK master slave flipflop. (8)
Or
(b) Explain in detail the operation of a 4 bit binary ripple counter. (16)
14. (a) Implement the following Boolean functions with a PLA
( ) ( ) ∑ = 4 , 2 , 1 , 0 , , 1 C B A F
( ) ( ) ∑ = 7 , 6 , 5 , 0 , , 2 C B A F
( ) ( ) ∑ = 7 , 5 , 3 , 0 , , 3 C B A F . (16)
Or
(b) Design a combinational circuit using a ROM. The circuit accepts a three
bit number and outputs a binary number equal to the square of the input
number. (16)
15. (a) Design a three bit binary counter using T flipflops. (16)
Or
(b) Design a negative-edge triggered ‘T flipflop’. (16)
