EE6301 DIGITAL LOGIC CIRCUITS SYLLABUS FOR 3RD SEM EEE DEPARTMENT REG-2013

EE6301 DIGITAL LOGIC CIRCUITS SYLLABUS FOR ANNA UNIVERSITY THIRD SEMESTER ELECTRICAL AND ELECTRONICS ENGINEERING EEE DEPARTMENT STUDENTS

EE6301 DIGITAL LOGIC CIRCUITS SYLLABUS

• University : Anna university
• Semester : 3rd sem
• Department : EEE
• Year : Second Year
• Regulation : 2013
• Subject Name : DIGITAL LOGIC CIRCUITS 
• Subject Code : EE6301
• Subject Credits : 4

EE6301 DIGITAL LOGIC CIRCUITS SYLLABUS

SYLLABUS

REGULATION 2013

OBJECTIVES:

• To study various number systems , simplify the logical expressions using Boolean functions 
• To study implementation of combinational circuits 
• To design various synchronous and asynchronous circuits. 
• To introduce asynchronous sequential circuits and PLCs 
• To introduce digital simulation for development of application oriented logic circuits. 

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code0- Digital Logic Families ,comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family

UNIT II COMBINATIONAL CIRCUITS 

Combinational logic - representation of logic functions-SOP and POS forms, K-map representations- minimization using K maps - simplification and implementation of combinational logic - multiplexers and demultiplexers - code converters, adders, subtractors.

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS

Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters -

asynchronous and synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state assignment.

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES

Asynchronous sequential logic circuits-Transition table, flow table-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits-introduction to Programmable Logic Devices: PROM – PLA –PAL.

UNIT V VHDL

RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages –Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flipflops, FSM, 

Multiplexers /Demultiplexers).

TOTAL (L:45+T:15): 60 PERIODS

OUTCOMES:

Ability to understand and analyse, linear and digital electronic circuits. 

TEXT BOOKS:

1. Raj Kamal, ‘ Digital systems-Principles and Design’, Pearson Education 2nd edition, 2007. 

2. M. Morris Mano, ‘Digital Design with an introduction to the VHDL’, Pearson Education, 2013. 

3. Comer “Digital Logic & State Machine Design, Oxford, 2012. 

REFERENCES:

1. Mandal ”Digital Electronics Principles & Application, McGraw Hill Edu,2013. 

2. William Keitz, Digital Electronics-A Practical Approach with VHDL,Pearson,2013. 

3. Floyd and Jain, ‘Digital Fundamentals’, 8th edition, Pearson Education, 2003. 

4. Anand Kumar, Fundamentals of Digital Circuits,PHI,2013. 

5. Charles H.Roth,Jr,Lizy Lizy Kurian John, ‘Digital System Design using VHDL, Cengage, 2013. 

6. John M.Yarbrough, ‘Digital Logic, Application & Design’, Thomson, 2002. 

7. Gaganpreet Kaur, VHDL Basics to Programming, Pearson, 2013. 

8. Botros, HDL Programming Fundamental, VHDL& Verilog, Cengage, 2013.

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